Cadence University Program Member


General Information

The Jack Baskin School of Engineering at the University of California, Santa Cruz is licensed for Level 1 of the Cadence University Software Bundles. This licensing is generously provided by Cadence Design Systems University Program at substantial educational discount. University licensing provides Baskin School of Engineering faculty and students access to the Cadence Design Software products listed below. Note that this page only contains information about Cadence products only; please refer to the appropriate software support page for information about other vendors' software.

The School currently supports the use of Cadence Software products on the Red Hat Linux and Microsoft Windows operating systems. Use of other operating systems is not supported nor recommended.

Technical Assistance

DO NOT contact Cadence Design Systems directly - all questions and requests must be submitted via the official site technical liaisons. Cadence Design Systems provides the software at a generous discount provided the site technical liaisons handle all questions and requests.

Should you have any questions related to the use of Cadence Design Systems Software, please send them to Please note in the subject line that your request is related to Cadence software.

E-Mail Questions and Problems:
Primary Technical Liaison: Eric Shell
Secondary Technical Liaison: Jose Renau
University Licensing Professor: Jose Renau

Course and Research Lab Use

Cadence software is used by the Baskin School of Engineering in a number of labs and classes. Should you wish to learn about practical usage of Cadence products, please contact the faculty, researchers and students in these courses and labs. This web page describes only how Cadence products are utilized at the Baskin School of Engineering and does not provide detailed instructions on how to use the tools themselves.

Cadence software products are often used in the following classes. This is a partial listing, as courses in the School of Engineering are constantly updated. Recommended courses for an introduction to some of the Cadence products include Computer Engineering 174 and Computer Engineering 222.

Undergraduate Courses

Graduate Courses

Cadence products are used in the following School of Engineering faculty research labs:

SPB/OrCAD Self-Serve Installation

Users can install OrCAD themselves using the following instructions.  These steps assume you have administrator rights on your system.  If you do not have local administrator rights you will not be able to install OrCAD.  If you are on a supported BSOE computer and do not have administrator rights, you should request help with the installation through the IT Request ticketing system.

  1. In a web browser, connect to and log in with your CruzID Blue credentials
  2. If you are not able to access that location but you are enrolled in a BSOE course or are otherwise affiliated with BSOE, please e-mail for assistance.
  3. You will see a set of files including an installation.txt file with installation instructions; please refer to that file for installation steps
  4. When installation has completed you can freely delete the installation files that you downloaded

Please note that if you are not on the BSOE network, either because you are off campus or in another part of campus, you will also need to connect to the UCSC VPN service before you will be able to check out a license and run Cadence software.

Specific Product Licensing

The School of Engineering is licensed for the following Cadence Design Systems Products.

Bundles Products  
Custom IC Bundle Software    

Design Environment
Virtuoso® analog design environment
Virtuoso® AMS Designer environment
Virtuoso® specification driven environment (VSDE)
Virtuoso® characteriszation & Modeling option for VSDE
Virtuoso® NeoCircuit DFM
Design Entry
Cadence SKILL Development environment
Virtuoso® schematic VHDL interface
Virtuoso® schematic editor Verilog® interface
Virtuoso® schematic editor
Virtuoso® analog Oasis run-time option
Virtuoso® Compactor
Virtuoso® -XL layout editor
Virtuoso® customer placer
Cadence® chip assembly router
Virtuoso® NeoCell analog physical synthesis
Physical Verification
Dracula® Graphical user interface
Cadence® RC Network reducer option
Dracula® physical verification and extractor suite
Cadence® chip assembly router
Diva® physical verification and extractor suite
Assura™ Design Rule checker
Assura™ layout vs. schematic verifier
Assura™ parasitic extractor
Assura™ RCX field solver option
Assura™ RCX mulitiprocessor option
Assura™ RCX high frequency option
Assura™ RF Bundle
Assura™ RCX RCX Parasitic Inductance: Cell Level Option
Assura™ Graphical User Interface Option
Assura™ multiprocessor option
RCX Advanced process features
Pcell Generator
Graphical Technology Editor
Generator for Assura™compatible verification decks
Generator for Diva® compatible verification decks
Generator for Dracula® compatible verification decks
Circuit Simulation
Virtuoso® Schematic editor HSPICE interface
Virtuoso® Schematic editor Spectre® interface
Virtuoso® electronic design for manufacturability option
Cadence® SPICE
Virtuoso® Spectre® analog circuit simulator
Virtuoso® UltraSim full chip simulator
Virtuoso® Spectre® RF simulation option
Virtuoso® analog HSPICE interface option
Virtuoso® AMS designer simulator
Virtuoso® Schematic composer to design complier integration
Virtuoso® EDIF 200 reader
Virtuoso® EDIF 200 writer
Virtuoso® EDIF 300 connectivity reader/writer
Virtuoso® EDIF 300 schematic reader/writer
Cadence® design framework integrator's toolkit

Digital Integrated Circuits Bundle    
  Place & Route and Timing
Virtuoso® -XL layout editor
Cadence® chip assembly router
Silicon Ensemble TM PKS optimization
Physical Verification
Dracula® physical verification and extractor suite
Design for Manufacturing
Fire & Ice QXC (gate)
VoltageStorm (gate and transistor)
Signal Integrity
CeltIC NDC crosstalk analyzer with delay calculator
PacifIC static noise analyzer for custom digital ICs
SignalStorm NDC nanometer delay calculator
SignalStorm library characterizer
Silicon Virtual Prototyping
Cadence® SOC Encounter Global Physical Synthesis (GPS)
Route accelerator multi-threaded route option
Encounter® test architect XL
Encounter® true time test GXL
Encounter® diagnostics GXL
Verification Bundle    
  Functional Verification
Cadence® NC-Verilog R simulator
Cadence® NC-VHDL simulator
Cadence® NC-Sim mixed language simulator
Cadence® simulation analysis environment
Incisive TM unified simulator
AMS option to Incisive
FormalCheck® model checker
Verification Process Automation
SpecMan Elite
Incisive™ enterprise manager
Incisive™ enterprise eAnalyzer
Formal Verification
Encounter™ Conformal GXL
Encounter™ RTL Compiler Ultra
Pre-verified, Re-usable Verification IP Components
AMBA AHB protocol
USB protocol
PCI Express End Point protocol
PCI Express Root Complex protocol
PCI 2.2/2.3 protocol
PCI-X 1.0/2.0 protocol
Ethernet protocol
AMBA AXI protocol
Silicon-Package-Board Bundle    
  PCB Design and Layout
Allegro® PCB librarian 610
Allegro® PCB design HDL 610
Allegro® PCB design CIS 610
PCB High-Speed Analysis
Allegro® PCB SI 610
IC Packaging
Allegro® Package Designer 620
Allegro® Package SI 620
Orcad Family
Allegro® PCB design HDL 220
Allegro® PCB design CIS 220
Allegro® AMS simulator 210
Layout Studio


Information is provided 'as is' without warranty of any kind. No statement is made and no attempt has been made to examine the information, either with respect to interoperability, origin, authorship, or otherwise. Please use this information at your own risk. We recommend using it on a copy of your data to be sure you understand what it does under your conditions. Keep your master intact until you are satisfied with the use of this information within your environment.

Cadence is a registered trademark of Cadence Design Systems, Inc., 2655 Seely Avenue, San Jose, CA 95134. This page is not an advertisement for Cadence products.

Page last updated 6/11/18.