Cadence University Program Member - BSOE Computing Support

General Information

The Jack Baskin School of Engineering is licensed for Level 1 of the Cadence University Software Bundles. This licensing is generously provided by Cadence Design Systems University Program at substantial educational discount. University licensing provides School of Engineering faculty and students access to the Cadence Design Software Products listed below. It is important to note that "Cadence" is the name of the company. Students do not learn "Cadence", rather they learn about Cadence Products. This web page only provides Cadence Design system information, information on any other vendor's products is not shown on this page.

The School currently supports operation of Cadence Software products on Sun Solaris, Redhat Linux and Microsoft Windows Computer systems. Use of other operating systems is not supported nor recommended.

Technical Assistance

DO NOT contact Cadence Design Systems directly - all questions and requests must be submitted via the official site technical liaisons. Cadence Design Systems provides the software at a generous discount provided the site technical liaisons handle all questions and requests.

Should you have any questions related to the use of Cadence Design Systems Software, please send them to help@ucsc.edu. Please put "SOE Services->3rd party software" in the title of the trouble ticket type, add Cadence to the Subject.

E-Mail Questions and Problems:	help@ucsc.edu
Primary Technical Liaison:	Derek Pearson
Secondary Technical Liaison:	Professor Matthew Guthaus
University Licensing Professor:	Professor Arthur Ramirez Dean of the Jack Baskin School of Engineering

Course and Research Lab Use

Cadence software is used by the Baskin School of Engineering in several labs and classes. Should you wish to learn about practical Cadence Products, please contact the faculty, researchers and students in these courses and labs. This web page describes only the use of Cadence products and does not provide detailed instructions on how to use them.

Cadence Design software products are often used in the following classes. This is a partial listing, as courses in the School of Engineering are constantly updated. Recommended courses for an introduction to some of the Cadence Products include Computer Engineering 174 and Computer Engineering 222.

Undergraduate Courses

Electrical Engineering 070/L - Introduction to Electronic Circuits
Electrical Engineering 115- Introduction to Micro-Electro-Mechanical-Systems (MEMS) Design
Electrical Engineering 123A- Senior Thesis - Electrical Engineering Design I
Electrical Engineering 123B - Senior Thesis - Electrical Engineering Design I
Electrical Engineering 171/L - Analog Electronics
Computer Engineering 121/L - Microprocessor System Design
Computer Engineering 123A - Senior Thesis / Computer Engineering Design I
Computer Engineering 123B - Senior Thesis / Computer Engineering Design II
Computer Engineering 170 - Circuits, Devices and Systems
Computer Engineering 174 - Introduction to EDA Tools

Graduate Courses

Electrical Engineering 211 - Introduction to Nanotechnology
Electrical Engineering 215 - Micro-Electro-Mechanical Systems (MEMS) Design
Electrical Engineering 221 - Advanced Analog Integrated Circuits
Computer Engineering 221 - Advanced Microprocessor Design
Computer Engineering 222 - VLSI Digital System Design
Computer Engineering 223 - VLSI System On a Chip design
Computer Engineering 226 - Computer-Aided Analysis of Electrical Circuits
Computer Engineering 227 - Advances in Computer-Aided Synthesis of VLSI Circuits

Cadence products are used in the following School of Engineering faculty research labs:

Updated 6/29/12

Biometric Microelectronic Systems Engineering Research Center (BMES ERC)
Advanced Integrated Electronics Research Group
Computer Aided Design Lab
Kestrel Parallel Processor
Nanoelectronic Circuits and Systems Lab
Micro-Architecture Santa Cruz

Specific Product Licensing

The School of Engineering is licensed for the following Cadence Design Systems Products.
A detailed listing of licensed Cadence Design Products is at: CadenceSoftwareListing
A current listing of licenses and checkouts can be viewed at: SOE License Watcher

Bundles	Products
Custom IC Bundle Software
	Design Environment Virtuoso® analog design environment Virtuoso® AMS Designer environment Virtuoso® specification driven environment (VSDE) Virtuoso® characteriszation & Modeling option for VSDE Virtuoso® NeoCircuit DFM Design Entry Cadence SKILL Development environment Virtuoso® schematic VHDL interface Virtuoso® schematic editor Verilog® interface Virtuoso® schematic editor Virtuoso® analog Oasis run-time option Layout Virtuoso® Compactor Virtuoso® -XL layout editor Virtuoso® customer placer Cadence® chip assembly router Virtuoso® NeoCell analog physical synthesis Physical Verification Dracula® Graphical user interface Cadence® RC Network reducer option Dracula® physical verification and extractor suite Cadence® chip assembly router Diva® physical verification and extractor suite Assura™ Design Rule checker Assura™ layout vs. schematic verifier Assura™ parasitic extractor Assura™ RCX field solver option Assura™ RCX mulitiprocessor option Assura™ RCX high frequency option Assura™ RF Bundle Assura™ RCX RCX Parasitic Inductance: Cell Level Option Assura™ Graphical User Interface Option Assura™ multiprocessor option RCX Advanced process features Pcell Generator Graphical Technology Editor Generator for Assura™compatible verification decks Generator for Diva® compatible verification decks Generator for Dracula® compatible verification decks Circuit Simulation Virtuoso® Schematic editor HSPICE interface Virtuoso® Schematic editor Spectre® interface Virtuoso® electronic design for manufacturability option Cadence® SPICE Virtuoso® Spectre® analog circuit simulator Virtuoso® UltraSim full chip simulator Virtuoso® Spectre® RF simulation option Virtuoso® analog HSPICE interface option Virtuoso® AMS designer simulator *Interfaces* Virtuoso® Schematic composer to design complier integration Virtuoso® EDIF 200 reader Virtuoso® EDIF 200 writer Virtuoso® EDIF 300 connectivity reader/writer Virtuoso® EDIF 300 schematic reader/writer Cadence® design framework integrator's toolkit
Digital Integrated Circuits Bundle
	*Place & Route and Timing* Virtuoso® -XL layout editor Cadence® chip assembly router Silicon Ensemble TM PKS optimization Physical Verification Dracula® physical verification and extractor suite *Design for Manufacturing* Fire & Ice QXC (gate) VoltageStorm (gate and transistor) Signal Integrity CeltIC NDC crosstalk analyzer with delay calculator PacifIC static noise analyzer for custom digital ICs SignalStorm NDC nanometer delay calculator SignalStorm library characterizer Silicon Virtual Prototyping Cadence® SOC Encounter Global Physical Synthesis (GPS) Route accelerator multi-threaded route option Test Encounter® test architect XL Encounter® true time test GXL Encounter® diagnostics GXL
Verification Bundle
	*Functional Verification* Cadence® NC-Verilog R simulator Cadence® NC-VHDL simulator Cadence® NC-Sim mixed language simulator Cadence® simulation analysis environment Incisive TM unified simulator AMS option to Incisive FormalCheck® model checker Verification Process Automation SpecMan Elite SureCov Incisive™ enterprise manager Incisive™ enterprise eAnalyzer Formal Verification Encounter™ Conformal GXL Synthesis Encounter™ RTL Compiler Ultra Pre-verified, Re-usable Verification IP Components AMBA AHB protocol USB protocol PCI Express End Point protocol PCI Express Root Complex protocol PCI 2.2/2.3 protocol PCI-X 1.0/2.0 protocol Ethernet protocol AMBA AXI protocol
Silicon-Package-Board Bundle
	*PCB Design and Layout* Allegro® PCB librarian 610 Allegro® PCB design HDL 610 Allegro® PCB design CIS 610 PCB High-Speed Analysis Allegro® PCB SI 610 IC Packaging Allegro® Package Designer 620 Allegro® Package SI 620 Orcad Family Allegro® PCB design HDL 220 Allegro® PCB design CIS 220 Allegro® AMS simulator 210 Layout Studio

Disclaimers

Information is provided 'as is' without warranty of any kind. No statement is made and no attempt has been made to examine the information, either with respect to interoperability, origin, authorship, or otherwise. Please use this information at your own risk. We recommend using it on a copy of your data to be sure you understand what it does under your conditions. Keep your master intact until you are satisfied with the use of this information within your environment.

Cadence is a registered trademark of Cadence Design Systems, Inc., 2655 Seely Avenue, San Jose, CA 95134. This page is not an advertisement for Cadence products.